1 . Field of the Invention
The present invention relates to embedded decoupling capacitors, particularly for silicon on insulator (SOI) technology, which reduce noise and help solve edge cell proximity effect problems, thereby, eliminating the need for separate decoupling capacitors and OPC structures.
2 . Description of the Related Art
Modern society places ever increasing demands on microelectronics technology. Today, chips are already functioning at speeds approaching the gigahertz range and current trends continue to demand that chips process increasing amounts of electronic signals using less space and less time. Chips are widely used in a variety of applications such as personal computers, memory banks, cell phones, and other electronic devices well known to those skilled in the art. Regardless of the exact application, the structure of the chip controls the speed at which the chip may function and the quantity of electronic signals that the chip can process.
Each chip has a semiconductor substrate with thousands of circuits that store and process electronic signals. To meet the ever increasing demand for high speed and high signal volume microelectronics, the number of circuits on the chips is increased. However, the number of circuits, and thus, advances in microelectronics, is limited by the availability of space on the surface of the chips.
The space on the chip is limited by two suboptimization features of the circuits on the chip. First, to reduce the noise resulting from the high speed data transmission, blocks of circuits require decoupling capacitors. Decoupling capacitors are relatively large structures and are used between a power supply and ground to provide enough noise immunity for proper circuit operation. For example, FIG. 1 is a simple diagram showing a buffer cell 10, a power supply 12 and noise 11 on the power line that is damped by a large decoupling capacitor 14.
Second, devices require at least two outer optical proximity correction (OPC) structures to reduce the optical diffraction effects caused by a change in the proximity environment at the edge of a line of active gates. The OPC structures are arranged by a process to correct the full chip layout data set. This process may be performed after a chip layout is generated by a technique called optical proximity correction or during the design process the OPC structures may be placed at either end of the line of the active gates in the circuits. In this position, the OPC structures reduce proximity effects by providing the active gates with the same local environment as the active gates in the middle of an array of gates. The use of OPC structures on the periphery of an array is an acceptable solution for stand-alone array chips or even for Application Specific Integrated Circuit (ASIC) chips where the array elements form a small fraction of the total chip area because the relative amount of space occupied by the OPC structures is small.
To optimize chip processing speeds and increase the amount of data processed, there is a need to effectively use space on the surface of the chips. As a result, it is advantageous to integrate decoupling capacitors and OPC structures without increasing noise or diffraction effects.
It is, therefore, an object of the present invention to provide a structure and method for providing a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.
A further embodiment of the invention is a semiconductor device, which includes a substrate, a first transistor having a first plurality of parallel elongated gates, the first transistor formed in a region of the substrate, and at least one OPC structure formed coplanar with and extending parallel to an outermost gate of the first plurality of elongated gates, wherein the OPC structure acts as a decoupling capacitor and an optical proximity corrector. The first plurality parallel elongated gates may have a same line width as the OPC structure, wherein the OPC structure reduces proximity effects of the first cells and the first plurality of parallel elongated gates is adapted to store and process data. The OPC structure may have a width greater than one gate of the first plurality of parallel elongated gates. The first transistor comprises multiple OPC structures and whereby the transistor comprises multiple decoupling capacitors. Each gate of the first plurality of parallel elongated gates of first cells is separated by a first distance, and the OPC structure is separated from the first plurality of parallel elongated gates by the first distance.
The invention further embodies a semiconductor device which includes a first region having first cells for storing and processing data wherein each of the first cells comprise devices separated by a first distance, and a second region outside the first region having OPC structures wherein the OPC structures are parallel and coplanar to an outermost device in a first cell of the first cells and one of the OPC structures is separated from the outermost first cell by the first distance, wherein the OPC structures comprise decoupling capacitors. The first cells comprise a same or similar line width as the OPC structures. The OPC structures reduce proximity effects of the first cells and further comprise a N-type FET and a P-type FET, wherein the N-type FET and the P-type FET each comprise the first region and the second region. The OPC structures may comprise a width greater than a width of the first cells, and the second region may comprise multiple OPC structures whereby the second region comprises multiple decoupling capacitors.